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VCXO Jitter Attenuator and FemtoClockTM Multiplier
ICS810252BI-03
DATA SHEET
GENERAL DESCRIPTION
The ICS810252BI-03 is a member of the TM family of high performance clock HiPerClockSTM HiperClockS solutions from IDT. The ICS810252BI-03 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock frequency multiplier that provides the low jitter, TM high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-TQFP, E-Pad and 32VFQFN packages and supports industrial temperature range.
FEATURES
* Two LVCMOS/LVTTL outputs, 17 impedance Each output supports independent frequency selection at 25MHz, 62.5MHz, 125MHz, and 156.25MHz * Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz * Attenuates the phase jitter of the input clock by using a lowcost pullable fundamental mode VCXO crystal * VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection * FemtoClock frequency multiplier provides low jitter, high frequency output * Absolute pull range: 50ppm * FemtoClock VCO frequency: 625MHz * RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz - 20MHz): 1.1ps (typical) * 3.3V supply voltage * -40C to 85C ambient operating temperature * Available in lead-free (RoHS 6) package
nCLK0 nCLK1 CLK0 CLK1 VDD
IC S
XTAL_OUT
PIN ASSIGNMENT
VDDX
32 31 30 29 28 27 26 25 LF1 LF0 ISET GND CLK_SEL VDD RESERVED GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PDSEL_2 PDSEL_1 PDSEL_0 VDDA VDD ODBSEL_1 ODBSEL_0 ODASEL_1
ICS810252BI-03
32-Lead TQFP, E-Pad 7mm x 7mm x 1.0mm package body Y package Top View 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View
ICS810252BYI-03 REVISION A AUGUST 20, 2009
XTAL_IN
24 23 22 21 20 19 18 17
GND VDDO_QB QB GND VDDO_QA QA GND ODASEL_0
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ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
BLOCK DIAGRAM
Loop Filter
XTAL_IN
ISET
LF0
LF1
PDSEL_[2:0] PU
3
XTAL_OUT
Output Divider 00 = 25 01 = 5 10 = 4 11 = 10
QA
VCXO Input Pre-Divider
nCLK0 CLK0 PD PU/PD
25MHz
0
CLK1 PD nCLK1
PU/PD
1
CLK_SEL Pulldown
000 = 1 001 = 193 010 = 256 011 = 2430 100 = 3125 101 = 9720 110 = 15625 111 = 19440
Phase Detector
VCXO
Charge Pump
FemtoClock PLL 625MHz
PD
2
ODASEL_[1:0]
VCXO Feedback Divider /3125
Output Divider 00 = 25 01 = 5 10 = 4 11 = 10
PD 2
QB
VCXO Jitter Attenuation PLL
ODBSEL_[1:0]
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ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3 4, 8, 18, 21, 24 5 6, 12, 27 7 9, 10, 11 13 14, 15 16, 17 19 20 22 23 25 26 28 29 30, 31 32 Name LF1, LF0 ISET GND CLK_SEL VDD RESERVED PDSEL_2, PDSEL_1, PDSEL_0 VDDA ODBSEL_1, ODBSEL_0 ODASEL_1, ODASEL_0 QA VDDO_QA QB VDDO_QB nCLK1 CLK1 nCLK0 CLK0 XTAL_OUT, XTAL_IN VDDX Type Analog Input/Output Analog Input/Output Power Input Power Reser ved Input Power Input Input Output Power Output Power Input Input Input Input Input Power Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Pullup Pulldown Description Loop filter connection node pins. Charge pump current setting pin. Power supply ground. Input clock select. When HIGH selects CLK1/nCLK1. When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels. Core power supply pins. Reser ved pin. Do not connect. Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A.
Analog supply pin. Frequency select pins for Bank B output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Frequency select pins for Bank A output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Bank A single-ended clock output. LVCMOS/LVTTL interface levels. 17 output impedance. Output power supply pin for QA clock output. Bank B single-ended clock output. LVCMOS/LVTTL interface levels. 17 output impedance. Output power supply pin for QB clock output. Inver ting differential clock input. VDD/2 bias voltage when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 bias voltage when left floating. Non-inver ting differential clock input. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Power supply pin for VCXO charge pump.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance Test Conditions Minimum Typical 4 VDD, VDDX, VDDO_QA, VDDO_QB = 3.465V 10 51 51 17 Maximum Units pF pF k k
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VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
TABLE 3A. PRE-DIVIDER FUNCTION TABLE
Inputs PDSEL_2 0 0 0 0 1 1 1 1 PDSEL_1 0 0 1 1 0 0 1 1 PDSEL_0 0 1 0 1 0 1 0 1 Pre-Divider Value 1 193 256 2430 3125 9720 15625 19440 (default)
TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE
Inputs ODxSEL_1 0 0 1 1 ODxSEL_0 0 1 0 1 Output Divider Value 25 (default) 5 4 10
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VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
TABLE 3C. FREQUENCY FUNCTION TABLE
Input Frequency (MHz) 0.008 0.008 0.008 0.008 1.544 1.544 1.544 1.544 2.048 2.048 2.048 2.048 19.44 19.44 19.44 19.44 25 25 25 25 77.76 77.76 77.76 77.76 125 125 125 125 155.52 155.52 155.52 155.52 Pre-Divider Value 1 1 1 1 193 193 193 193 256 256 256 256 2430 2430 2430 2430 3125 3125 3125 3125 9720 9720 9720 9720 15625 15625 15625 15625 19440 19440 19440 19440 VCXO Frequency (MHz) 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 Femtoclock VCO Frequency (MHz) 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 625 Output Divider Value 25 5 4 10 25 5 4 10 25 5 4 10 25 5 4 10 25 5 4 10 25 5 4 10 25 5 4 10 25 5 4 10 Output Frequency (MHz) 25 125 156.25 62.5 25 125 156.25 62.5 25 125 156.25 62.5 25 125 156.25 62.5 25 125 156.25 62.5 25 125 156.25 62.5 25 125 156.25 62.5 25 125 156.25 62.5
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ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 32 Lead VFQFN 37C/W (0 mps) 32 Lead TQFP 32.2C/W (0 mps) Storage Temperature, TSTG -65C to 150C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO_QA, VDDO_QB VDDX IDD + IDDX IDDA IDDO_QA + IDDO_QB Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Charge Pump Supply Voltage Power and Charge Pump Supply Current Analog Supply Current Output Supply Current No Load Test Conditions Minimum 3.135 VDD - 0.13 3.135 3.135 Typical 3. 3 3.3 3.3 3.3 Maximum 3.465 VDD 3.465 3.465 190 13 2 Units V V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage Input High Current CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] PDSEL[0:2] CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] PDSEL[0:2] VOH VOL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 2.6 0.5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 15 0 5 Units V V A A A A V V
IIH
IIL
Input Low Current
NOTE 1: Outputs terminated with 50 to VDDO_QA,_QB/2.
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VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK0/nCLK0, CLK1/nCLK1 CLK0, CLK1 nCLK0, nCLK1 Test Conditions VIN = VDD = 3.465V VIN = 0V, VDD = 3.465V VIN = 0V, VDD = 3.465V -5 -150 0.15 GND + 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 Units A A A V V
Peak-to-Peak Input Voltage; NOTE 1
VCMR Common Mode Input Voltage; NOTE 1, 2 NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 5. AC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V5%, TA = -40C TO 85C
Symbol fIN fOUT Parameter Input Frequency Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Skew; NOTE 2, 3 Output Duty Cycle 125MHz, 25MHz cr ystal Integration Range: 12kHz - 20MHz 47 Test Conditions Minimum 0.008 25 1.1 130 53 Typical Maximum 155.52 156.25 Units MHz MHz ps ps %
tjit(O) tsk(o)
odc t R / tF
Output Rise/Fall Time 20% to 80% 20 0 500 ps VCXO & FemtoClock PLL Reference Clock Input is 50ppm 3 s tLOCK Lock Time; NOTE 4 from Nominal Frequency NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized with outputs at the same frequency using the loop filter components for the high loop bandwidth. Refer to VCXO-PLL Loop Bandwidth Selection Table. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage, same frequency and with equal load conditions. Measured at VDDO/2. NOTE 4: Lock time measured from power-up to stable output frequency.
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VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
TYPICAL PHASE NOISE AT 125MHZ
125MHz
RMS Phase Jitter (Random) 12kHz to 20MHz = 1.1ps (typical)
NOISE POWER dBc Hz
OFFSET FREQUENCY (HZ)
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VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.65V5%
VDD
VDD, VDDO_QA, VDDO_QB, VDDA VDDX LVCMOS
GND
SCOPE
Qx nCLK0, nCLK1
V
PP
Cross Points
V
CMR
CLK0, CLK1
GND
-1.65V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
Phase Noise Plot
V
DDO_Q
FOUTx
Noise Power
2
V
DDO_Q
FOUTy
2 tsk(o)
f1
Offset Frequency
f2
RMS Jitter = Area Under Offset Frequency Markers
PHASE JITTER
OUTPUT SKEW
V
DDO_Q
QA, QB t PW
t
PERIOD
2
80% 20% tR
80% 20% tF
QA, QB
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
OUTPUT RISE/FALL TIME
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ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
PARAMETER MEASUREMENT INFORMATION, CONTINUED
VCXO & FEMTOCLOCK PLL LOCK TIME
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached.
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ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS810252BI-03 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDX, VDDA, VDDO_QA and VDDO_QB should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDX .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLKx
V_REF nCLKx C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
2.5V
3.3V
2.5V 3.3V 2.5V
*R3
33
Zo = 50
R3 120 Zo = 60
R4 120
CLK
CLK
Zo = 50 nCLK
Zo = 60 nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER
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ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE)
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ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
TQFP EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.
SOLDER PIN EXPOSED HEAT SLUG
SOLDER
PIN
SOLDER
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
FIGURE 5. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE)
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ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
LAYOUT GUIDELINE
Figure 6 shows an example of the 810252IB-03 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. An
VDD R11 125 R13 125
optional 3-pole filter can also be used for additional spur reduction. It is recommended that the loop filter components be laid out for the 3-pole option. This will also allow the 2-pole filter to be used.
Zo = 50
CLK1 nCLK1
Zo = 50 R12 84 VDD R7 125 R9 125 R14 84
LVPECL Driv er
VDD = VDDX = VDDO_QA = VDDO_QB = 3.3V
Zo = 50
CLK0 nCLK0
Zo = 50 R8 84 LVPECL Driv er R10 85 C28 3pf 25MHz, CL =10pf XTAL_IN VDD C29 3pf R26 C47 0.01u 10 VDDX CLK0 nCLK0 XTAL_OUT
C28 and C29 are used for additional capacitance to center VCXO tuning curve. For most layouts, it is recommended to add an additional 3pf. For boards with high parasitics, C28 and 29 might not be required.
VDD
C15 0.1u
U1
32 31 30 29 28 27 26 25
C46 10u
R1 VDDO_QB VDDO_QA 35
Zo = 50 Receiv er
2-pole loop filter example
LF0 Rs 221k VDD Cs 0.1uF Cp 0.001uF LF1 LF1 LF0 LF1 LF0 GND CLK_SEL 1 2 3 4 5 6 7 8 LF1 LF0 ISET GND CLK_SEL VDD nc GND
VDDX XTAL_IN XTAL_OUT CLK0 nCLK0 VDD CLK1 nCLK1
GND VDDO_QB QB GND VDDO_QA QA GND ODASEL_0 PDSEL_2 PDSEL_1 PDSEL_0 VDD VDDA ODBSEL_1 ODBSEL_0 ODASEL_1
24 23 22 21 20 19 18 17
GND GND R2 GND ODASEL_0 35 Receiv er Zo = 50
C12 0.1u
R20 2.21K ICS810252BI-03
3-pole loop filter example - (optional)
R3 LF0 Rs 200k Cs 1.0uF Cp 0.01uF 820k C3 220pF VDDA C14 0.1u C30 0.01u C45 10u LF1 VDD ODBSEL_1 ODBSEL_0 ODASEL_1 PDSEL_2 PDSEL_1 PDSEL_0
9 10 11 12 13 14 15 16
VDDO_QB
VDDO_QA
C17 0.1u
C18 0.1u
R25
10 VDD
FIGURE 6. SCHEMATIC OF RECOMMENDED LAYOUT
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VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependant on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The frequency of oscillation in the third overtone mode is not necessarily at exactly three times the fundamental frequency. The mechanical properties of the quartz element dictate the position of the overtones relative to the fundamental. The oscillator circuit may excite both the fundamental and overtone modes simultaneously. This will LF0 cause a nonlinearity in the LF1 tuning curve. This potential ISET problem is the reason VCXO RS RSET crystals are required to be CP CS tested for absence of any activity inside a 200ppm window at three times the XTAL_IN fundamental frequency. Refer to CTUNE FL_30VT and FL_30VT_SPURS in the Crystal 25MHz Characterization Table.
XTAL_OUT CTUNE The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components.
The crystal's load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE).
If the crystal CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal CL is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than
VCXO CHARACTERISTICS TABLE
Symbol kVCXO CV_LOW CV_HIGH Parameter VCXO Gain Low Varactor Capacitance High Varactor Capacitance Typical 8000 8 17 Unit Hz/V pF pF
VCXO-PLL LOOP BANDWIDTH SELECTION TABLE
Bandwidth 10Hz (Low) 50Hz (Mid) 125Hz (High) Crystal Frequency (MHz) 25MHz 25MHz 25MHz RS (k ) 120 221 620 CS (F) 1.0 0.1 0.022 CP (F) 0.01 0.001 0.0004 RSET (k ) 8.8 2.21 2.21
CRYSTAL CHARACTERISTICS
Symbol fN fT fS CL CO CO /C1 FL_30VT FL_30VT_SPURS ESR Parameter Mode of Operation Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio 3rd Over tone FL 3rd Over tone FL Spurs Equivalent Series Resistance Drive Level Aging @ 25C
ICS810252BYI-03 REVISION A AUGUST 20, 2009 16
Minimum
Typical 25
Maximum
Units MHz
Fundamental 20 20 -40 10 4 220 200 200 40 1 3 per year mW ppm
(c)2009 Integrated Device Technology, Inc.
ppm ppm C pF pF
85
240
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS810252BI-03. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS810252BI-03 is the sum of the core power plus the analog plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Core Power Dissipation * Power (core)MAX = VDD_MAX * ((IDD + IDDX) + IDDA) = 3.465V * (190mA + 13mA) = 703.4mW Output Power Dissipation * Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 17)] = 25.9mA * Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 17 * (25.9mA)2 = 11.4mW per output * Total Power Dissipation on the ROUT Total Power (ROUT) = 11.4mW * 2 = 22.8mW Dynamic Power Dissipation at 125MHz Power (125MHz) = CPD * Frequency * (VDDO)2 = 10pF * 125MHz * (3.465V)2 = 15mW per output Total Dynamic Power (125MHz) = 15mW * 2 = 30mW Total Power Dissipation * Total Power = Power (core)MAX + Total Power (ROUT) + Total Dynamic Power (125MHz) = 703.4mW + 22.8mW + 30mW = 756.2mW
2. Junction Temperature. Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.756W * 37C/W = 113C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of terminated outputs, supply voltage, air flow, and the number of board layers. FOR 32 LEAD VFQFN, FORCED CONVECTION TABLE 6A. THERMAL RESISTANCE
JA
JA vs. 0 Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
TABLE 6B. JA VS. AIR FLOW TABLE
FOR
32 LEAD TQFP, E-PAD
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 32.2C/W
1
26.3C/W
2.5
24.7C/W
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(c)2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
3. Case Temperature calculated from Junction Temperature JC Calculations In applications where there is a heatsink present, and the majority of the power is dissipated through the top of the device, the junction temperature can be calculated from the case temperature, TC, using the junction-to-case thermal resistance value JC. In practical application is it the average of the case temperature of the surface of the device on which the heatsink is attached.
The equation for calculating the junction temperature is as follows: Tj = JC * Pd_case + TC Tj = Junction Temperature JC= Junction-to-Case Thermal Resistance Pd_case = Total Device Power Dissipation through the case TC = Average Case Temperature It is important to emphasize that case temperature calculations using JC do not use Pd_total, rather they use Pd_case, which is the portion of power dissipated through the case. In real applications it is difficult to quantify the power dissipated through the case, so the value of JC is best used for a package-to-package comparison, rather than a junction temperature calculation. As such, the JEDEC standard (JESD51-2) uses another parameter, JT (PsiJT), which can be used to calculate junction temperature from a measured case temperature. JT Calculations JT is the thermal characterization parameter which reports the differences between junction temperature and the temperature at the top dead center of the outside surface of the component package, divided by the power applied to the component. This requires knowing the total power dissipation and a measured case temperature in order to calculate the junction temperature. It can also be calculated using an estimated case temperature for a given junction temperature. In the following equation, TT, is used to indicate the single-point temperature measurement at the top-center of the case. The change in the naming convention from TC to TT is to differentiate the use between the JC and JT calculations. The equation for TJ is as follows: Solving for TT yields: TJ = TT + JT * Pd_total TT = TJ - JT * Pd_total
TJ = Junction Temperature JT = (PsiJT) Junction-to-Top of Package Parameter Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TT = Temperature at the top-center of the package
The advantage of this method is that it allows for the calculation of the junction temperature or case temperature using total power dissipation and eliminates the need to quantify power dissipation through the top of the device. In order to calculate TT, the appropriate JT factor must be used. Assuming no air flow, a multi-layer board, and E-Pad soldered to the board, the appropriate value is 0.3C/W per Table 7 below. Therefore, TT for a TJ value of 113C (from the example in section 2) with all outputs switching is: TT = 113.0C - 0.756W * 0.3C/W = 112.8C. This calculation is only an example. TJ will vary depending on the number of terminated outputs, supply voltage, air flow and the number of board layers.
Table 7. JT for 32 Lead VFQFN, Forced Convection
JT by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 0.3C/W
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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(c)2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
RELIABILITY INFORMATION
TABLE 8A. JAVS. AIR FLOW TABLE
FOR
32 LEAD VFQFN
JA vs. 0 Air Flow (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.0C/W
1
32.4C/W
2.5
29.0C/W
TABLE 8B. JAVS. AIR FLOW TABLE
FOR
32 LEAD TQFP, E-PAD
by Velocity (Meters per Second)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards 32.2C/W
1
26.3C/W
2.5
24.7C/W
TRANSISTOR COUNT
The transistor count for ICS810252BI-03 is: 6597
ICS810252BYI-03 REVISION A AUGUST 20, 2009
19
(c)2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP, E-PAD
-HD VERSION EXPOSED PAD DOWN
TABLE 9A. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS ABA-HD SYMBOL N A A1 A2 b c D, E D1, E1 D2, E2 e L ccc D3 & D3 0.45 0 -3.0 --3.5 -0.05 0.95 0.30 0.09 MINIMUM NOMINAL 32 -0.10 1.0 0.35 -9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.75 7 0.10 4.0 1.20 0.15 1.05 0.40 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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(c)2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN
S eating Plan e Ind ex Area N Anvil Singula tion A1 A3 L N 1 2 E2 (N -1)x e
E2 2
(Re f.) (Ref.)
(N -1)x e
(R ef.)
N &N Even
e (Ty p.) 2 If N & N
are Even
OR
To p View
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9B below.
(Ref.)
e D2 2 D2
N &N Odd
Th er mal Ba se
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of
TABLE 9B. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL N A A1 A3 b ND NE D D2 E E2 e L 0.30 3.0 3.0 5.00 BASIC 3.15 5.00 BASIC 3.15 0.50 BASIC 0.40 0.50 3.3 3.3 0.18 0.80 0 MINIMUM NOMINAL 32 --0.25 Ref. 0.25 0.30 8 8 1.00 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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(c)2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
TABLE 10. ORDERING INFORMATION
Part/Order Number 810252BKI-03LF 810252BKI-03LFT 810252BYI-03LF 810252BYI-03LFT Marking ICS252BI03L ICS252BI03L ICS0252BI03L ICS0252BI03L Package 32 Lead "Lead-Free" VFQFN 32 Lead "Lead-Free" VFQFN 32 lead "Lead-Free" TQFP, E-Pad 32 lead "Lead-Free" TQFP, E-Pad Shipping Packaging tray 2500 tape & reel tray 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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(c)2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
REVISION HISTORY SHEET Rev A T9B 21 Table Page 16 Description of Change VCXO-PLL External Components - replace 2nd to last paragraph. Cr ystal Characteristics Table - add 3rd Over tone specs. VFQFN Package Dimensions - corrected D2/E2 dimensions. Date 8/20/09
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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(c)2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER
www.IDT.com
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitablity of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Techology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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